LA/OC SMTA is Proud to Present an
Educational and Networking Event...

Chapter Dinner Meeting
Member Appreciation Night

Design for Testability (DFT)

Louis Y. Ungar
Advanced Test Engineering (A.T.E.) Solutions, Inc.

Design for Testability (DFT) is like good weather - people talk about it and welcome it, but feel they have no control over it. Actually, they do. The SMTA put together a set of Testability Guidelines more than a decade ago, and we have since revised it a few times and the SMTA made it available for under $100 for companies to purchase. Following those guidelines, electronics manufacturers could save hundreds of thousands, perhaps millions of dollars each year. But they don’t. The IEEE put out DFT boundary scan standards in 1990 that are just now (26 years later) getting some traction. The IPC is coming out with a DFX standard. Will that catch on? Eventually… perhaps. Why is there stagnation or even resistance to a process that simply makes designers conscious of testing requirements and difficulties? As circuits get more compact, increase in complexity and become less accessible to probing, we will have to increasingly conclude that they are not testable. Whether a non-testable circuit works in the user environment or not is a crapshoot. With over 5 billion Internet of Things (IoT) products/year coming from production, that gamble translates to 50 million faulty circuits if only 1% are faulty. But with the crapshoot, maybe 10% will be faulty, requiring us to service 500 million (1/2 billion) bad products a year. Discarding that many pieces of electronics is not only costly but environmentally prohibitive. DFT is no longer a test engineering or design engineering concern. It is time to bring this issue before every manager in the organization. Producing so much garbage should be a concern for everyone. In this presentation we will look at who and how other disciplines need to view testability issues from product conception through design, manufacturing, deployment, use, prognosis, repair, redeployment and finally discarding.

Mr. Ungar enjoys a well-known reputation in the electronics testing profession. He has built, programmed, and selected Automatic Test Equipment (ATE) for a large number of clients both in the commercial and military community. Having introduced the first university course on ATE and Design for Testability (DFT) at UCLA, he has taught similar courses to companies around the world. He led the Surface Mount Technology Association (SMTA) Testability Committee to publish the SMTA Testability Guidelines from 2002 with the most recent 2014 SMTA Testability Guidelines. He has been involved with the IEEE standards committee for several DFT standards, including the IEEE-1149.1, the 1149.4 and the 1687 and has been honored as a life-time member of the American Society of Test Engineers and is the Tutorial Chair of the IEEE AutoTestCon. He is involved with the IPC-2231 standard for DFX, where X is substituted for
Testability, Reliability, Manufacturability, etc. He is also the co-author of a technical paper on False Alarms and No Fault Found that won the Best Management Paper award at AutoTestCon 2015. Mr. Ungar completed courses towards a MA in Management and holds a BS degree in Electronics Engineering and Computer Sciences from UCLA. He continues teaching DFT and BIST courses at conferences, at companies and at public forums around the world.

Thursday, May 19th, 2016
(3rd Thursday of the Month)

6:00PM, Social Hour
7:00PM, Dinner/Presentation

Cash or Check
$15, Members
$35, Nonmembers

Paypal Payment
(Fee + 2.9% + .30 Processing Fee)
$15.75, Members
$37, Nonmembers

Does not Include Beverages

JT Schmid's Restaurant & Brewery

2610 E. Katella Avenue
Anaheim, California 92806

Driving Directions

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Walk-Ins are welcome, but reservations when possible help us plan better.
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Hope to see you there!